This invention relates to floating gate memory circuits such as EPROMs and flash memory devices. This invention also relates to floating gate memory output circuits.
Typical EPROMs comprise an array of floating gate transistors such as transistor 1 which is selectively coupled to a biasing circuit 2 and a first input lead 3 of a sense amplifier 4. When it is desired to read the data stored in transistor 1, the voltage at control gate 5 is raised, e.g. to about 5 volts. If the floating gate of transistor 1 is electrically neutral, the voltage at input lead 3 will drop when the voltage at control gate 5 increases, whereas if the floating gate is negatively charged, the voltage at input lead 3 will not drop. Sense amplifier 4 compares the voltage at input lead 3 with a reference voltage V.sub.ref provided by a reference voltage generator 6 and generates therefrom an output signal on an output lead 7 in response thereto. The signal on output lead 7 is communicated via a tri-state buffer 8 to an output pin 9.
One of the most important performance parameters of an EPROM is the propagation delay between the time a signal is applied to input lead 3 and the time an output signal is provided on pin 9 by buffer 8. Specifically, it is desirable to minimize the propagation delay.
One technique for minimizing the propagation delay time of an EPROM is to construct EPROM cells comprising two floating gate transistors. The first transistor stores a first binary value while the second transistor stores a second value opposite the first value. The drain of the first and second transistors are coupled, via biasing circuitry, to a differential sense amplifier. It has been found that circuits constructed in this manner provide fast access times. Such circuits are discussed by Zeman et al. in "A 55ns CMOS EEPROM", published at the 1984 IEEE International Solid-State Circuits Conference, pages 144-145 and by Pathak et al. in "A 25ns 16k CMOS PROM Using a 4-Transistor Cell", published at the 1985 IEEE Solid-State Circuits Conference, pages 162-163, incorporated herein by reference. Unfortunately, memory cells employing two or more transistors are large and thus expensive to build. It would be desirable to obtain fast EPROM access times without using a multiple transistor cell.